The density of dynamic random access memories (DRAMs), which are usually used as main memory devices in computer systems, has increased about four-fold every three years, and efforts toward their high speed operation and lower power consumption have successively been made. High speed operation of DRAMs is desired to reduce the operating speed gaps between the DRAM and processors, and especially their lower power consumption is required for portable devices. Examples of DRAMs intended to achieve high speed operation include synchronous DRAMs using a system clock and a rambus DRAM by Rambus, Inc. Also, DRAMs aim at low power consumption for portable devices using batteries, such as portable computers, mobile phones, or the like.
Since data stored in a memory cell of the DRAM disappears (discharges) with the lapse of time, the memory cell data must periodically be recharged. Such operations are commonly referred to as "refresh operations". The refresh operations are typically classified into an ROR refresh, a hidden refresh, a CBR(CAS before RAS) refresh, and an extended CBR (ECBR) refresh operation in accordance with the performance manner. The difference between the CBR refresh operation and the ROR refresh operation as mentioned above is that in the ROR refresh operation the word line selection is made by the address given by a controller, but in the CBR refresh operation only a CBR refresh input signal is received from the controller and remaining operations are executed by an on-chip internal circuit. Compared with the ROR refresh operation, the CBR refresh operation has the advantage of lessening the burden of the controller. A latch operation of a row address for selecting a word line is executed by a toggling of a row address strobe signal RAS.
Recently, a self-refresh operation which still more extends the ECBR refresh operation is widely used. The self-refresh operation reduces to a maximum extent the power consumption in a DRAM device in order to extend the operating time of the computer system using a battery. In case where an access to a DRAM is not performed for a long time, the DRAM enters a self-refresh operation mode and suppresses to a maximum extent the operation of the DRAM to reduce the power consumption of the DRAM. For example, if a laptop computer is used for a word processing work in an airplane, since a constant level of power is not supplied to the computer, the computer used on boarding should be operable for a long time without interruption by the battery installed therein. A very important concern is not the processing speed of the computer, but the extension of time available for use of the computer by suppressing power consumption. That is, it is important how long the usage time of the computer can be extended without loss of data stored in the DRAM. Further, in other systems, and particularly when the DRAM is not accessed, the reduction of the power consumption by the DRAM is very important.
The self-refresh operation of a DRAM is executed in the following manner. Generally, a self-refresh input signal is made up of combination of a CBR and a timer output. When a CBR cycle is set up, a normal operation is halted and a refresh mode begins. Here, word line selection is sequentially made not by an external address but by a counter installed in the interior of a chip. Further, a data output operation to the exterior of the chip is not performed and only a cell data restoring operation in the interior of the chip is performed.
FIG. 1 is a timing diagram showing operating voltage V.sub.OP and bit line precharge voltage V.sub.BL variation in accordance with execution of the refresh operation of the prior art and the present invention. After a refresh mode is started by the CBR cycle, if the signal RAS is not toggled during a given time period (for example, about 100 microsecond), the self-refresh operation begins. In order to reduce the power consumption of a DRAM during the refresh mode, the operating voltage V.sub.OP used in the DRAM is lowered to a voltage V.sub.RFH level from a first power supply voltage V.sub.CC level, as shown in FIG. 1, and then the self-refresh operation is performed. Hereinafter, the voltage V.sub.RFH is referred to as a second power supply voltage. And, before exiting the self-refresh mode, the operating voltage V.sub.OP is recovered from the second power supply voltage V.sub.RFH to the first power supply voltage V.sub.CC, and one or more refresh cycles are performed during a time period of tA in FIG. 1.
Data `1` is stored in one memory cell of the DRAM by use of the first power supply voltage V.sub.CC level during the normal operation and the CBR refresh operation, while the data `1` is stored in the memory cell by use of the second power supply voltage V.sub.RFH level during the self-refresh operation. Before the refresh operation is completed, at least one refresh cycle is performed during the time period tA after the operating voltage V.sub.OP goes to the second power supply voltage V.sub.RFH from the first power supply voltage V.sub.CC. At this time, there may arise one problem described below in detail.
In general, several hundreds of memory cells each consisting of a storage capacitor and an access transistor are connected to a bit line. Assuming that a bit line loading is about 175 Farad and a loading of one storage capacitor is about 25 Farad. Under this assumption, when one memory cell is selected, charge sharing between the storage capacitor and a bit line connected to the selected memory cell occurs. A voltage level on a bit line previously precharged (typically, half of the first power supply voltage V.sub.CC, that is, V.sub.CC /2) is changed due to the charge sharing. A voltage variation .DELTA.V.sub.BL on the bit line is sensed and amplified by a sense amplifier (refer to FIG. 3). The voltage variation .DELTA.V.sub.BL (or, a sense margin of a sense amplifier circuit 150 in FIG. 3) can be expressed by a following equation. ##EQU1##
Here, the denotation V.sub.CELL indicates a voltage corresponding to data stored in the selected memory cell and the denotation V.sub.BL indicates a bit line precharge voltage. As well-known in the art, the bit line precharge voltage V.sub.BL level corresponds to half of the first power supply voltage V.sub.CC, that is, V.sub.CC /2. If data `1` is stored in the memory cell when the first power supply voltage V.sub.CC as the operating voltage V.sub.OP is supplied, then a voltage level of the data `1` is the first power supply voltage V.sub.CC level, but if data `0` is stored therein, then a voltage level of the data `0` is a ground voltage V.sub.SS level. Under this assumption that data `1` is stored in the selected memory cell, a voltage variation .DELTA.V.sub.BL on a bit line associated with the memory cell is: ##EQU2##
In the former case, a voltage level on a precharged bit line increases by the voltage variation .DELTA.V.sub.BL in equation (2), and in the latter case, the voltage level on the precharged bit line decreases by the voltage variation .DELTA.V.sub.BL in equation (2). Thereafter, the bit line voltage variation .DELTA.V.sub.BL, i.e., the difference between the bit line pair associated with the selected memory cell, is detected by a sense amplifier circuit (refer to 150 in FIG. 3).
But, it is one problem of the prior art that read malfunction for data `1` occurs during a refresh operation during a time period tA shwon in FIG. 1. The more increased the difference between the first power supply voltage V.sub.CC and the second power supply voltage V.sub.RFH, the higher the probability of such a read malfunction for data `1`.
As mentioned above, before the refresh operation is performed, data `1` is stored in the selected memory cell using the first power supply voltage V.sub.CC level. When the self-refresh operation is executed, the data `1` is restored using the second power supply voltage V.sub.RFH level lower than the voltage V.sub.CC level. As mentioned above, one or more refresh cycles are performed during the time period tA before existing the refresh mode. At this time, the bit line is precharged to a voltage level corresponding to half of the first power supply voltage V.sub.CC, and data `1` is restored using the second power supply voltage V.sub.RFH level during the self-refresh mode.
Under this condition, if a refresh operation is performed during the time period tA, a sense amplifier may not sense and amplify a voltage difference .DELTA.V.sub.BL between a bit line pair associated with the memory cell in which the data `1` is stored. That is, a voltage variation .DELTA.V.sub.BL of one bit line connected to a storage capacitor through an access transistor in the selected memory cell becomes lower: ##EQU3##
Because the voltage variation .DELTA.V.sub.BL in equation (3) is lower than that in equation (2), it may not be sensed by the sense amplifier (refer to FIG. 3). This causes the read malfunction for the data `1` during the time period tA. The larger a difference between the first power supply voltage V.sub.CC and the second power supply voltage V.sub.RFH and the variation of the operating voltage V.sub.OP, the smaller the bit line voltage variation .DELTA.V.sub.BL (or, the sense margin of a sense amplifier 150 in FIG. 3). It can be understood that this causes a higher possibility of the read malfunction. Referring to FIG. 2, as the second power supply voltage V.sub.RFH becomes lower, read fail for data `1` is concentrated in right lower part. To improve this, if the bit line precharge voltage V.sub.BL during the normal operation is made lower than that during the self-refresh operation, then there may arise another problem that a sense margin for data `0` is decreased, inducing read malfunction for the data `0`.